The circuits using a programmable array have been developed as ASIC (application specified ICs), that is, as small-quantity products or trial products. Conventionally, the typical circuits using the programmable array are GAs (gate arrays) and SCs (standard cells) customized from the mask level so as to satisfy the specifications required by the user, or PLAs (programmable logic arrays) customized by the user itself. In the case of the SCs, logic circuit blocks used in an LSI (Large Scale Integration) are previously registered in a computer, and products required by the user are designed by arranging and connecting these logic circuit blocks through the automatic processing by use of the computer. Further, in the case of the GAs, basic circuits for constituting logic gates are previously formed into an array pattern on a semiconductor substrate, and the user manufactures any desired LSI by deciding the wiring pattern using an automatic wiring. Software in the same way as with the case of the standard cells. The above-mentioned methods have such advantages that the period required for development is relatively short, as compared with the ordinary LSI which is totally designed from the beginning. In these methods, however, there still exists a problem in that it takes several weeks or several months from the design end to the production completion, because the manufacturing process is still required after the user has finished the design. In other words, in the case of the GAs and SCs, although there exists such an advantage that any required circuits can be realized, a long development period is needed and thereby the development cost is relatively higher than that of the PLAs. In contrast with this, in the case of the PLAs, although the cost is low and the development period is short, there exists a limit in the actually realizable circuits.
To overcome the shortcomings involved in both the circuit devices, recently, a circuit device referred to as FPGA (field programmable gate array) has been developed, by which any given circuits (as with the case of the GAs) can be developed by the user (as with the case of the PLAs). In this FPGA, there are previously arranged basic cells (each composed of a single of or a plurality of transistors), interconnections for connecting these basic cells, and programmable elements, so that any desired circuits can be obtained by the user by programming these programmable elements. As this circuit device, various devices provided with different programmable elements and different basic cells are now being developed.
Here, the FPGA which uses anti-fuses as one example of the above-mentioned programmable elements will be explained hereinbelow, in which the anti-fuses are arranged at the intersections between the crosswise arranged wires connected to logic blocks so that the interconnections can be connected to or disconnected from each other.
FIG. 1 shows the FPGA using anti-fuses A as the programmable elements. When any desired anti-fuses A are selectively programmed, it is possible to obtain any desired logic circuit. The respective anti-fuses A are provided at the intersections between a group LG1 of first wires C arranged in the vertical direction and a group LG2 of second wires R arranged in the horizontal direction, respectively. The first and second wires C and R intersect each other in three dimensions. These wire groups are referred to as wiring resources sometimes hereinbelow. Under non-programmed conditions, the first and second wires are disconnected from each other by the respective anti-fuses A as shown in FIG. 2(a). Under programmed conditions, on the other hand, the first and second wires are connected to each other by the respective anti-fuses A as shown in FIG. 2(b). When an anti-fuse A is not yet programmed, the white circle (NP) as shown in FIG. 1(a) is used; and when an anti-fuse A is programmed, the black circles (P) as shown in FIG. 1(b) is used, hereinafter.
FIGS. 3(a) to (c) show only the anti-fuses existing at the respective intersections between the wire groups (in which the logic blocks LB are omitted) for assistance in explaining the programming procedure. When the anti-fuse A22 is required to be programmed under the non-programmed conditions as shown in FIG. 3(a), a programming potential VPP is applied to the wire C2; a ground potential GND is applied to the wires R2; and an intermediate potential VPP/2 is applied to the other wires, respectively as shown in FIG. 3(b). In this case, since the potential not high enough to program the anti-fuses is applied across the non-selected anti-fuses but the potential high enough to program the anti-fuse is applied across the selected anti-fuse A22, it is possible to selectively program the selected anti-fuse A22. Successively, when the anti-fuse A21 is required to be programmed as shown in FIG. 3(c), the programming potential VPP is applied to the wire C1; the ground potential GND is applied to the wire R2; and the intermediate potential VPP/2 is applied to the other wires, respectively. In this case, however, an excessive current flows from the intermediate potential to the ground potential through the programmed anti-fuse A22 (for connecting the wires R2 and C2). This current increases in proportion to the number of the programmed anti-fuses. Consequently, in the conventional FPGA using the anti-fuses, there exist problems in that the current consumption is large during the programming stage and thereby the desired potentials are not applied to the wire groups, with the result that the selected anti-fuses cannot be programmed.
FIG. 8 shows the output portions of a plurality of the logic blocks having common input terminals G1 and G2 (or so programmed), and FIG. 9 shows the same circuit obtained when the respective logic blocks LB1 to LB6 are shown by use of MIL symbols. In FIG. 8, V1 and V2 are wires to which the supply potential and the ground potential are applied, respectively after having programmed. However, during the programming, these wires must be kept at a floating potential. The reason is as follows: in the logic blocks LB1, LB3, LB4 and LB6, since at least one of P-type and N-type field effect transistors for constituting the output portion is turned on irrespective of the potentials at the input terminals G1 and G2, there exists a possibility that the potentials applied to the wires R1, R3, R4 and R6 for programming are shorted to the supply potential or the ground potential so that the current consumption increases or the anti-fuses cannot be programmed normally.
Here, when the wires R1 and C2 are required to be connected to each other, as shown in FIG. 10 the ground potential GND is applied to the wire R1; the program potential VPP is applied to the wire C2; and an intermediate potential VPP/2 is applied to the other wires, respectively to break-down the insulation of the anti-fuse A12 for shorting the wires R1 and C2. Further, when the anti-fuse A62 is required to be programmed, as shown in FIG. 11 the program potential VPP is applied to the wire C2; the ground potential GND is applied to the R6; and the intermediate potential is applied to the other wires. In this case, however, there exist the following problems: since the anti-fuse A12 has been already shorted, the potential VPP is applied to both the wires R1 and C2, so that this potential VPP is outputted to the wire R6 through the wire V1 or V2 (because at least one of P-type and N-type field effect transistors for constituting the output portion is turned on irrespective of the potentials at the input terminals G1). In this case, however, since another ground potential GND is applied to the wire R6 separately, the programming potential VPP is shorted to the ground potential GND so that an excessive current flows. Further, in the worst case, the necessary programming potentials are not applied across the anti-fuse A62, so that it is impossible to program the programmable elements. To overcome this problem, the following restriction is required: the logic blocks having the common input terminals cannot be used; or the outputs of the logic blocks must be programmed before the inputs of the logic blocks are programmed for connecting, thus arising another problem in that the circuit constitution and the program procedure are both restricted.
In addition, in the above-mentioned FPGA LSI, since the internal wires are not connected to one another before programmed, in case some defects (e.g., disconnection between the wires, short-circuits to other portions, etc.) occur in the LSI, there exists a possibility that the circuit will not operate normally in accordance with the user's design, in spite of the fact that the program procedure has been completed properly. As a result, in the conventional FPGA LSI, it has been indispensable to test the presence or absence of the disconnections and short-circuits of the wiring resources from and to other portions, before shipping, to omit the defective products. In the case of the above-mentioned test, since voltage must be applied to one end of each of all the wires to measure current flowing from one end to the other end of all the wires; or else since the potential must be applied between the wires to be tested and the other wires adjacent to or crossing the wire to be tested for current measurement, there exists another problem in that it takes a long test time (since the current must be measured by an external instrument) and thereby the manufacturing cost thereof is high.
In summary, in the conventional FPGA using the anti-fuses, there exist such drawbacks that when the anti-fuses are required to be programmed after some anti-fuses have been programmed, the current consumption increases; erroneous programming occurs; the circuit must be constituted under due consideration of the influence of the programmed anti-fuses; and the program procedure must be restricted. In addition, there exists a problem in that the programmed circuit cannot be realized for some the circuits designed by the user, and a long test time is required to test the disconnection or the short-circuit of the wiring resources.